These teachings relate generally to sigma-delta (SD) modulators of a type used in data converters and, more specifically, relate to the use of SD-based converters in equipment that places different demands on the performance and operation of the SD converter. Even more specifically, these teachings are directed to the data conversion of audio and RF signals at a digital baseband interface for enabling further processing either for RF transmission or for digital signal processing.
SD modulators used in analog-to-digital converters (ADCs) are well known in the art. Reference may be had, by example, to S. R. Norsworthy et al., xe2x80x9cDelta-Sigma Data Convertersxe2x80x9d, IEEE Press, NY, 1997, and to J. G. Proakis et al., Digital Signal Processingxe2x80x9d Third Edition, Prentice-Hall, 1996.
Currently several air interface standards for mobile communications devices, such as cellular telephones, are in wide use, and the signal bandwidth and dynamic range are different in each standard. In one possible data conversion solution each of the RF-baseband (analog-to-digital (AD) and digital-to-analog (DA)) interfaces uses dedicated RF AD/DA converters with certain optimum numbers of bits and sampling rates for each targeted system and radio architecture. Furthermore, when one mobile communication device is required to support more than one standard, then more than one RF DA/AD converter will typically be required, e.g., one for each supported standard. This, however, results in an increased hardware cost and overhead.
Additionally, the conversion performance is typically designed according to predetermined worst-case signal conditions. This results in an overhead in performance under most usage conditions, which in turn can result in increased power consumption. For battery powered devices, such as typical cellular telephones and personal communicators, any increase in power consumption is detrimental to the goal of extending the talk and standby times.
A single-bit second-order sigma-delta modulator with a digital decimation filter is widely used for audio and RF converters. The virtues of the single-bit sigma-delta technique include a high achievable linearity and a wide dynamic range. However, these benefits come at the cost of a required high over-sampling ratio (OSR) and, therefore, increased current consumption. Due to stability reasons the highest practical order of the sigma-delta modulator is limited to two, and any possibilities for providing configurability by changing the order of the sigma-delta modulator are limited. Thus, the only practical parameter for configuring or adapting the sigma-delta modulator is the over-sampling ratio. However, in order to obtain a wide dynamic range a high over-sampling ratio is required.
As is known, oversampling analog-to-digital converters two parts: an analog modulator and a digital filter. The analog modulator receives an analog signal and produces a serial data stream having a bit rate which is much greater than the Nyquist sampling frequency. The quantization noise of the analog modulator is shaped to minimize the noise in the passband of interest, at the expense of higher noise outside of this passband. This is as opposed to distributing the noise evenly between DC and the modulator sampling frequency. The digital filter portion of the ADC is operable to filter and decimate the modulator representation of the analog input. Since the modulator quantization noise is shaped, the digital filter must filter this out-of-band quantization noise and reduce the output word frequency to the desired final sample frequency. Decimation is a well-known technique that is utilized in most oversampling ADCs.
Typically, oversampling ADCs utilize a fixed decimation filter architecture (usually SINC filters in combination with FIR filters) to realize a desired filter transfer function, and the decimation filter is arranged to reduce the sampling frequency of a digital information signal step-by-step such that no aliasing occurs. Various structures and embodiments of decimation filters are known. The common practice is to use one or several SINC filters in the first stage(s) due to their simplicity and efficiency, and to use FIR filters in the final stages. The order of the SINC filter is typically one order higher than the sigma-delta modulator in order to filter out the spectrally shaped quantization noise. The decimation ratio of the SINC filter is usually chosen to be one-fourth of the total decimation ratio (or oversampling ratio OSR) due to the consideration of the attenuation at the upper end of the passband. The FIR filter performs the final decimation to the desired sample frequency, and defines and equalizes for the final desired frequency response.
FIG. 1 shows a typical sigma-delta ADC topology, where the output of the analog sigma-delta modulator 10 is connected to an input of a decimation filter 12. The modulator 10 typically employs a loop filter (10A) that feeds a quantizer 10B, and an analog feedback path that includes a DAC 10C. The quantizer 10B typically is a 1-bit quantizer for linearity purposes and is of second order for stability reasons. The modulator 10 over-samples at a sampling rate of Fs, and the resulting data stream is gradually stage-by-stage decimated by the over-sampling ratio (OSR) to a lower rate (Fs/OSR), but higher resolution, signal (N bits) in the decimation filter 12. In a typical case the decimation filter 12 includes a data register 12A, a multiply and accumulate (MAC) unit 12B and a coefficients register 12C.
Instead of 1-bit quantization, a 2-bit or higher resolution quantization is beneficial for at least two reasons: the dynamic range is increased by at least 6 dB /per additional bit, and higher order modulators can be used without incurring stability problems.
Multi-bit sigma-delta techniques thus provide an additional degree of freedom for the configuration and adaptation of a sigma-delta data converter. Configuration and adaptation by changing the number of bits is an effective means for setting the converter performance at a level required in certain conditions. This is also an effective technique for use with low over-sampling ratios, when changing the order of the sigma-delta modulator is not appropriate. The use of cascaded sigma-delta modulators offers a possibility for increasing the order of the sigma-delta modulator and for configuring the modulator to simultaneously meet the requirements of different standards, such as the second generation (2G) digital cellular standard and the third generation (3G) digital cellular standard. Reference with regard to cascaded modulators and to changing the modulator order can be had to U.S. Pat. No. 6,087,969 xe2x80x9cSigma-delta Modulator and Method for Digitizing a Signalxe2x80x9d, by Stockstad et al. However, when the over-sampling ratio is low the benefits of modifying the order of the sigma-delta modulator are only marginally effective in the most critical cases.
As was noted, the dynamic range is increased 6dB for each additional bit, and can be increased even further if the modulator coefficients are configured simultaneously. Therefore, in a performance-wise optimum configuration the modulator coefficients are changed each time the number of quantization levels (bits) is altered.
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.
These teachings are directed to an adaptive sigma delta modulator that avoids the use of several RF (and audio) SD converters in a mobile communication device that is intended to operate in accordance with several air interface standards and under various signal conditions. The use of these teachings achieves this goal by providing a single sigma-delta modulator-based AD and or DA converter that is constructed so as to be adaptable to different system requirements by changing at least the number of bits used in the SD modulator. The loop filter parameters of the SD modulator may also be altered as required, and certain of the stages may be controlled to operate at lower bias currents.
Further in accordance with these teachings it becomes possible to controllably reduce the performance of the RF and data conversion signal paths in a controlled manner, thereby reducing the typical performance overhead lowering power consumption to achieve longer total operating times.
These teachings provide a technique to achieve an optimal performance-to-power consumption ratio by altering the number of bits in the sigma-delta modulator, by modify the modulator loop filter coefficients and by configuring the bias current levels. In that it is not required to change the order of the sigma-delta modulator, thus the decimation or post-filter characteristics (e.g., steepness) are not required to be modified, and the filter structure may be maintained essentially the same in each sigma-delta modulator operational mode. Only a relatively minor reconfiguration may be needed, such as changing the word width.
In certain cases it is also possible to switch the operation of the sigma-delta modulator (in the ADC) from discrete time operation (using switched capacitor (SC) techniques) to continuous time operation (using resistor-capacitor (RC) techniques) in order to relax the bandwidth requirements of the operational amplifiers used in the sigma-delta modulator. This enables even further savings in power consumption. This technique can be accomplished by replacing each switched capacitor and its associated switches with a resistor.
These teachings thus provide, in a multi-mode and an adaptive data converter, the following features: (a) the number of bits used in the sigma-delta modulator may be changed according to the desired mode of operation, and (b) the number of bits used in the sigma-delta modulator may be changed dynamically during operation according to signal conditions (signal strength, the presence or absence of interferers etc.) In addition, the loop filter transfer function and coefficients may be changed to maintain an optimum dynamic range when the number of bits is changed. The bias currents may also changed. Furthermore, the circuit techniques (switched capacitor to resistor-capacitor or vice versa) may be changed as a function of the operational mode.
The use of further techniques, such as dynamic element matching (DEM), can be employed to linearize the operation of the sigma-delta modulator. When configuring and adapting the data converter to a certain level of performance the DEM algorithm may also be altered to, for example, one of the following types: noise-shaping, data weighted averaging (DWA), clocked averaging (CLA) or random DEM. In the most compact form of configuration for medium or low resolution data conversion the DEM algorithm may be turned off completely to conserve power.
The sigma-delta modulator configuration and adaptation techniques in accordance with these teachings are applicable to audio signals found in speech, wide-band speech and music reproduction, as well as to RF data conversion, in all types of the mobile communication systems.
Conventional mixed signal technology is used and enhanced with digital configuration blocks in accordance with an aspect of these teachings.
The use of these teachings thus avoid the requirement to provide several standard-specific data converters in a multi-standard mobile communication device, thereby reducing hardware overhead and conserving both silicon area and overall power consumption.
These teachings provide a solution for implementing multi-mode data (RF and audio) converters for multi-standard communication devices. In addition, altering the number of bits and the bias currents accordingly enables one to maintain optimized performance and power consumption in response to prevailing signal conditions. With the configurable multi-bit modulator the decimation filter may also be configured to have a variable word width.
In one aspect these teachings provide a multimode communications device that includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC comprising a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further comprising a multimode control function for programming the signal converter core as a function of a currently selected operational mode (e.g., 2G versus 3G system operation). The programmable signal converter core preferably includes a sigma-delta modulator, and there is further provided a signal analysis function for analyzing the received RF signal for dynamically programming the programmable signal converter core to adapt to temporary signal and interference conditions by one of increasing or decreasing the performance of the signal converter. The signal analysis function may be embodied as a decimation filter having an input coupled to an output of the sigma-delta modulator, or by a digital signal processor device that forms a portion of a baseband section.
The programmable signal converter core may be programmed to change the number of bits used by the sigma-delta modulator and/or a loop filter transfer function and loop filter coefficients, or a number of quantizer signal comparators or levels, or decimator coefficients and word width. The sigma-delta modulator bias currents may also be changed, as may a selected type of dynamic element matching function, each as a function of the selected mode. Other operational criteria that can be changed include, but are not limited to, the sigma-delta modulator oversampling ratio, and/or a change from a switched capacitor to a resistor-capacitor circuit technique, or vice versa.